RETORNNA – UNIZAR

Project developed by GaZ (Computer Architecture Group at the University of Zaragoza). This proyect aims to provide a full-fleged implementation of three machine learning acceleration techniques that could be seamlessly integrated into existing RISC-V cores, including both hardware and software support

Latest News

Sep 8, 2025 2 min read

Embench-IoT Results on GaZmusino

The performance of a microcontroller or RISC-V core can be measured in many ways, but Embench-IoT has become a reference benchmark for embedded systems and IoT applications. In this post, we compare the performance of our core GaZmusino, evaluated via simulation with Verilator, against the results reported by Antmicro on their Embench-Tester platform.

Aug 28, 2025 2 min read

Implementation of the Compressed Instruction Extension in GaZmusino

The RISC-V C compressed instruction extension reduces code size and improves memory efficiency without affecting core functionality. In this post, we explain how this extension has been integrated into GaZmusino and the benefits it brings in terms of performance and code density.

Jun 14, 2025 1 min read

GaZcache: A Fully Parametrizable Cache Memory

We are excited to introduce Gazcache, a cache memory designed to accelerate memory access and enhance the efficiency of any processor that employs it. This cache serves as a fast intermediate storage, supporting both data and instruction caching, and significantly reducing latency compared to main memory.

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Latest Publications

Samuel Pérez, Darío Suarez, Javier Resano (2024). Accelerating Bayesian Neural Networks on Low-Power Edge RISC-V Processors.

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Yamilka Toca-Díaz, Rubén Gran, Alejandro Valero (2024). Flip-and-Patch: A fault-tolerant technique for on-chip memories of CNN accelerators at low supply voltage.

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