Implementation of the Compressed Instruction Extension in GaZmusino
The RISC-V C compressed instruction extension reduces code size and improves memory efficiency without affecting core functionality. In this post, we explain how this extension has been integrated into GaZmusino and the benefits it brings in terms of performance and code density.
🔧 Integration Methodology
Modifications were made to the decode unit and pipeline to support 16-bit instructions alongside standard 32-bit instructions:
- The compressed instruction decoder from the cv32e40p was used as a starting point, removing instructions not supported by GaZmusino.
- A decode-stage instruction buffer was added, which can be read and written at the byte level, facilitating the selection of the correct instruction.
- Fetch and decode have independent PCs: the fetch PC always increments by +4, while the decode PC increments by +2 or +4 depending on whether the decoded instruction is compressed or standard.
- Functional tests were carried out using Verilator simulations to verify the correct execution of all compressed instructions.
📊 Benefits
- Reduced code size: programs occupy less flash memory, which is critical in resource-constrained embedded systems.
- Better cache utilization: by reducing the code footprint, instruction cache efficiency is improved.
- Reduced pipeline bubbles: the buffer is constantly filled even when the core is stalled in later stages, minimizing cycles where the pipeline is waiting for instructions.
Overall, these improvements allow GaZmusino to execute compressed code more efficiently, making better use of memory and the pipeline.
📝 Conclusions
- GaZmusino now supports the RISC-V C extension, increasing compatibility with modern software and tools.
- The integration allows for memory savings and cache efficiency without sacrificing critical operation performance.
- Next steps: measure the impact on real benchmarks (such as Embench-IoT) to quantify the improvements of compressed code versus standard code.